Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances

Electrical chip-to-chip interconnects suffer from considerable intersymbol interference at multi-Gb/s data rates, due to the frequency-dependent attenuation. Hence, reliable communication at high data rates requires equalization, to compensate for the channel response. As these interconnects are prone to manufacturing tolerances, the equalizer must be adjusted to each specific channel realization to perform optimally. We adopt a reduced-complexity equalization scheme where (part of) the equalizer is fixed, by involving the channel statistics into the equalizer derivation. For a 10 cm on-board microstrip interconnect with a 10% tolerance on its parameters, we point out that 2-PAM transmission using a fixed prefilter and an adjustable feedback filter, both with few taps, yields only a moderate bit error rate degradation, compared to the all-adjustable equalizer; at a bit error rate of 1e-12 these degradations are about 1.1  dB and 3  dB, when operating at 20 Gb/s and 80 Gb/s, respectively

Optimized precoded spatio-temporal partial-response signaling over frequency-selective MIMO channels

Due to the continuous demand for higher bit rates, the management of the spatio-temporal intersymbol interference in frequency-selective multiple-input multiple-output (MIMO) channels becomes increasingly important. For single-input single-output channels, equalized precoded partial-response signaling is capable of handling a large amount of intersymbol interference, but, to date, no equalization scheme with general partial-response signaling has been presented for the frequency-selective MIMO channel. Not only does this contribution extend partial-response signaling to the MIMO channel by proposing a general spatio-temporal partial-response precoder, but it also develops a minimum mean-squared-error optimization framework in which the equalization coefficients and the spatio-temporal target response are jointly optimized. Three iterative optimization algorithms are discussed, which update (part of) a row of the target impulse response matrix in each iteration. In particular, the third algorithm reformulates this row optimization as a lattice decoding problem. Numerical simulations confirm that the general partial-response signaling clearly outperforms the traditional full-response signaling in terms of the mean squared error and the bit error rate. The third optimization algorithm has a better performance but a higher complexity, compared to the first and the second algorithm

Robust spatio-temporal partial-response signaling over a frequency-selective fading MIMO channel with imperfect CSI

Partial-response signaling is known to facilitate the equalizer design because a controlled amount of residual interference is permitted. The design of the target impulse response of the partial-response precoder often assumes perfect channel state information, which is unfortunately not available at the transmitter in most practical applications. Consequently, this contribution focuses instead on the robust and joint design of a spatio-temporal target impulse response and the equalization coefficients for a frequency-selective fading multiple-input multiple-output communication channel based on current and/or previous noisy channel estimates. More precisely, the error in the channel estimates is statistically modeled, and robustness is achieved by minimizing the mean-squared estimation error averaged over the joint distribution of the actual channel and the available channel estimates. Numerical results of the bit error rate confirm that the proposed robust partial-response signaling not only provides a significant performance gain compared to traditional full-response signaling, but also outperforms the naive approach, which ignores channel estimation errors

MMSE equalization of multi-Gb/s chip-to-chip interconnects with M-PAM signaling affected by manufacturing tolerances

To further increase the communication speed on a chip-to-chip interconnect, more powerful equalization will be needed to reduce the considerable intersymbol interference caused by frequency-dependent attenuation. These interconnects however are prone to manufacturing tolerances, leading to equalization schemes that ideally are adjustable according to each specific realization. In this paper we make use of the minimum mean-square error criterion to obtain novel reduced-complexity equalizers, which have only some parts adjustable and the remaining parts fixed. These equalization schemes are compared with the all-adjustable equalizers in terms of mean square error and symbol error rate, for communication speeds of 20 Gbit/s and 120 Gbit/s. For a microstrip with 10% tolerance on its parameters, we point out that using a fixed pre-equalizer and an adjustable decision-feedback filter gives rise to only a minor symbol error performance degradation (less than about 1.5 dB), both for 2-PAM and 4-PAM signaling at both considered bit rates

MIMO time-domain equalization for high-speed continuous transmission under channel variability

High-speed communication over mutually coupled channels can be severely affected by intersymbol interference (ISI) and crosstalk (XT). Multiple-input multiple-output (MIMO) equalization is known to mitigate both ISI and XT, but requires accurate channel information at the receiver (RX) and/or transmitter (TX), when the channel is stochastic. However, since adjusting the equalization filters to the specific channel realization involves a considerable implementational and computational complexity, it is desirable to keep the equalization filters fixed irrespective of the specific channel realization, especially when the channel variability is relatively small. Therefore, we propose a general MIMO transceiver scheme where the equalization filters depend on the channel statistics rather than the actual channel. More specifically, by considering the time-domain equalization with the fixed linear MIMO pre-equalization and adjustable MIMO decision feedback equalization, the complexity associated with passing channel information from the RX to the TX is avoided, and the computationally intensive and iterative calculations of the fixed pre-equalizer can be performed offline rather than on-chip. The proposed equalization scheme is shown to yield only a small performance degradation compared to fully adjustable equalization schemes, thereby enabling multi-Gbit/s chip-to-chip communication over low-cost electrical interconnects which are prone to manufacturing tolerances